The present invention is directed to semiconductor devices and, more specifically, to semiconductor devices including thyristor structures and devices.
Recent technological advances in the semiconductor industry have permitted dramatic increases in integrated circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Presently, single-die microprocessors are being manufactured with many millions of transistors, operating at speeds of hundreds of millions of instructions per second and being packaged in relatively small, air-cooled semiconductor device packages. The improvements in such devices have led to a dramatic increase in their use in a variety of applications. As the use of these devices has become more prevalent, the demand for reliable and affordable semiconductor devices has also increased. Accordingly, the need to manufacture such devices in an efficient and reliable manner has become increasingly important.
An important part in the design, construction, and manufacture of semiconductor devices concerns semiconductor memory and other circuitry used to store information. Conventional random access memory devices include a variety of circuits, such as SRAM and DRAM circuits. The construction and formation of such memory circuitry typically involves forming at least one storage element and circuitry designed to access the stored information. DRAM is very common due to its high density (e.g., high density has benefits including low price), with DRAM cell size being typically between 6 F2 and 8 F2, where F is the minimum feature size. However, with typical DRAM access times of approximately 50 nSec, DRAM is relatively slow compared to typical microprocessor speeds and requires refresh. SRAM is another common semiconductor memory that is much faster than DRAM and, in some instances, is of an order of magnitude faster than DRAM. Also, unlike DRAM, SRAM does not require refresh. SRAM cells are typically constructed using 4 transistors and 2 resistors or 6 transistors, which result in much lower density, with typical cell size being between about 60 F2 and 150 F2.
Various SRAM cell designs based on a NDR (Negative Differential Resistance) construction have been introduced, ranging from a simple bipolar transistor to complicated quantum-effect devices. These cell designs usually consist of at least two active elements, including an NDR device. In view of size considerations, the construction of the NDR device is important to the overall performance of this type of SRAM cell. One advantage of the NDR-based cell is the potential of having a cell area smaller than four-transistor and six-transistor SRAM cells because of the smaller number of active devices and interconnections.
Conventional NDR-based SRAM cells, however, have many problems that have prohibited their use in commercial SRAM products. These problems include, among others: high standby power consumption due to the large current needed in one or both of the stable states of the cell; excessively high or excessively low voltage levels needed for cell operation; stable states that are too sensitive to manufacturing variations and provide poor noise-margins; limitations in access speed due to slow switching from one state to the other; limitations in operability due to temperature, noise, voltage and/or light stability; and manufacturability and yield issues due to complicated fabrication processing.
A thin capacitively-coupled thyristor-type NDR device can be effective in providing a bi-stable element for such memory cells and in overcoming many previously unresolved problems for thyristor-based memory applications. This type of NDR device has a control port that is capacitively coupled to a relatively-thin thyristor body. The thyristor body is sufficiently thin to permit modulation of the potential of the thyristor body in response to selected signals capacitively coupled via the control port. Such capacitively-coupled signals are used to enhance switching of the thyristor-based device between current-blocking and current-conducting states.
One method for manufacturing thyristor-type NDR devices (and other circuitry) is to form a vertical silicon pillar by first depositing a layer of silicon and subsequently masking and etching the deposited silicon layer. However, this approach typically makes it difficult to subsequently form planar MOSFET devices and others. For example, it is difficult to add STI (Shallow Trench Isolation) after etching the pillar since STI usually requires a chemical-mechanical polishing (CMP) step, which would be inhibited by the pillar. Patterning a mask (e.g., for photolithography) near such a pillar is also difficult because the resist has a tendency to form puddles. In addition, angled implants used after the formation of the pillar may introduce shadowing problems, with the pillar being implanted instead of the intended implantation of other devices near the pillar. Furthermore, implanting the pillar to form the thyristor, as well as masking horizontal devices such as source/drain regions of a MOSFET near the pillar, are also challenging.
These and other design considerations have presented challenges to the implementation of such a thin capacitively-coupled thyristor to bulk substrate applications, and in particular to applications where highly-dense arrays of thyristors are desirable.
The present invention is directed to a thyristor-based semiconductor device that addresses the above-mentioned challenges. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to a more general example embodiment, the present invention is directed to a method for manufacturing a semiconductor device having a substrate and in which a trench is formed with part of the thyristor being formed in a filled portion of the trench.
In a more specific example embodiment, a method for making a semiconductor device includes forming a semiconductor material in the trench, and forming a thyristor having adjacent regions of different polarity, with at least one of the regions including a portion of the formed semiconductor material in the trench and at least one other of the regions including a portion of the substrate that is adjacent the trench. A control port is then formed so that it couples control signals capacitively to one or more of the adjacent regions.
According to another example embodiment of the present invention, a thyristor-based semiconductor device includes a trench in a substrate used to form the thyristor. A semiconductor material is formed in the trench and used to form a thyristor having adjacent regions of different polarity. One or more of the regions includes a portion of the formed semiconductor material in the trench, and one or more of the regions includes a portion of the substrate that is adjacent to the trench. A control port is formed capacitively coupled to one or more of the regions. The thyristor can then be coupled to various other circuit elements, such as a pass gate used in a memory cell. With this approach, manufacturing and operational challenges to the formation of thyristor-based devices, including those challenges discussed above, are addressed.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description that follow more particularly exemplify these embodiments.